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The ASE Group's reputation has been built
on the development and application of cutting-edge technologies
such as fine pitch wire bonding, flip
chip, wafer bumping, wafer-level
CSP, multi stacked-die packaging, system
in package (SiP), and 300 mm wafer backend
assembly and testing . Long-term investment in research
and development has enabled us to stay ahead of the competition
in the application of new technologies.
As the industry leader, ASE was the first to achieve volume production for
wafer bumping, flip chip, chip scale package (CSP), stacked die package,
and system
in package (SiP) technology. Customers have benefited greatly from our
lead in advanced technology.
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| Fine Pitch Wire Bonding |
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ASE's fine-pitch bonding technology
features smaller solder balls and a finer pitch than
conventional BGA (ball grid array) solutions, enabling
the packaging of more circuits, such as baseband,
RF, microcontroller and memory onto a single chip.
ASE, a proven leader in fine pitch wire bonding technology, has the world's
largest capacity with over 3,400 fine-pitch wire bonders. We offer
single-in-line, 2-row-staggered and tri-tier and quad-tier wire bonding
services. ASE currently enjoys over 50% of outsourced-market share.
Our advanced fine pitch bonding technology is fully aligned with leading
fab roadmaps, enabling innovative IC manufacturing processes, which
include the most advanced 90-nanometer and down to 65-nanometer technology.
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| Flip Chip Technology |
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ASE has focused on developing flip
chip technology to meet the growing demand for packaging
solutions with increased I/O density, smaller size
and improved heat dissipation characteristics. ASE
is the first professional assembly service provider
to
offer a total flip chip solution under one-roof, from
packaging characterization, substrate design, wafer
bumping, wafer sort to assembly and final test, creating
the ultimate turnkey solution
with our 300mm wafer flip chip bumping service.
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ASE offers the widest
experience in handling different devices & BOM
combination as well as a professional assembly house
to assemble CPUs using flip chip technology.
We began the development process of flip chip technology much earlier
than our competitors and began mass production of flip chip packages in
2000, providing complete offerings of high performance and high quality
flip chip packages to meet customers' requirements ever since. |
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| Wafer
Bumping |
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Wafer bumping, an essential
process in flip chip packaging, is an advanced packaging
technique where 'bumps' or 'balls' made of solder
are formed on the wafers before being diced into
individual chips.
As the world's leading IC assembly house, ASE established its wafer
bumping services in 1999 and licensed its initial bumping process
from Kulicke & Soffa's Flip Chip Division. In 2001, in line with
the industry's transition to 300mm wafer fabrication, ASE
became the first independent assembly company to offer 300mm solder bumping
technology.
ASE has made a significant investment in wafer bumping research and development,
and necessary equipment. Our R&D team has also successfully qualified
its own electroplated bumping technology, becoming the leading independent
packaging
company to offer customers the choice of printed or
plated bumping technologies in-house for 150mm, 200mm and 300mm wafers.
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| Wafer
Level CSP |
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As many package types are converting from SO
(Small Outline) packages to CSP (Chip Scale Package)
solutions to meet performance requirements, ASE has
also become the leader in CSP packaging including wafer
level CSP. ASE's wafer level packaging solutions meet
the industry's burgeoning demand, as well as CSP trend
requirements for smaller and thinner chip scale packages.
ASE's Ultra CSP and
Polymer Collar WLP ,
licensed from Kulicke & Soffa's Flip Chip Division, are the ideal
solution by virtue of their real-die package size and thinness, while
providing the most cost-effective solution as most of the processes
are carried out on the wafer simultaneously.
To be compatible with existing wire-bone type dies, Ultra CSP and
Polymer Collar WLP can
redistribute pad layout by using thin film technology. In addition, to
achieve smaller form factor, the electrical performance is enhanced
due to trace path shrinkage.
ASE provides customers with a total turnkey solution for wafer level
packages including 6" and 8" wafers, from wafer bumping,
backend assembly, final test (both whole wafer and sawn wafer
test), and final tape and reel output, all under one roof to achieve
effective cycle time, delivering reliability in terms of quality and time-to-market.
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| System
in Package (SiP) |
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Demand for miniaturization and
increased functionality have brought system in package
(SiP) to the forefront of semiconductor developments.
Performing a sub-system function
at package level, SiP is more than just a multiple chip package with
dies laid out side by side
or stacked inside of encapsulant. SiP has evolved into a package comprising
integrated modules of several chip packages lined
up side by side or stacked, and through the
addition of passives or other required components, a fully functional
sub-system is created.
ASE was the first in the industry
to introduce its SCSP (Stacked CSP) and MPBGA (Multi-Package
Ball Grid Array) technologies in 2001. Aligning with
ASE's capability in integrated substrate services,
our SiP technology provides customers with optimal
electrical performance for high density design requirements.
Currently, we have volume production
of 5-die stacked packages and 3-package stacked modules.
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| Multi
Stacked-Die Packaging |
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continues the focus on its leading multi-stacked-die
packaging technology, drawing
from over three years of mass production experience in stacked-die packaging.
Our outstanding capabilities enable us to offer a wide range of high-density
packages like 2-die stacked CSP, sandwich stacked CSP, 3-die stacked
CSP, 4-die sandwich stacked CSP, 5-die stacked CSP, flip chip & wirebond
CSP, and MCM stacked CSP.
With expertise in advanced wafer thinning (minimum wafer thickness: 3
mil), an automatic handling system and epoxy control for thin die attach,
ASE is initiating more innovation in its multi-stacked-die packaging
to enable the integration of more functions into a single thinner and
smaller package.
Since taking lead in the industry to launch mass production of 1.4 mm
thick stacked CSP technology, ASE has consistently set the pace in
stacked die packaging technology. We have nearly 30 patents issued
and pending in multi stacked-die packaging technology and are confident
that ASE is the best partner to provide customers with all the experience
needed to assemble and test the highest density stacked-die packages.
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| 300mm Wafer Backend
Assembly and Testing |
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According to market forecast, 300mm wafer capabilities
are projected to account for 45% of total wafer production
by 2006, creating the value-added products of the future
such as processors, graphics, and communications chips.
To accommodate industry migration to 300mm wafer fabrication,
ASE's 300mm wafer handling equipment has already been
installed and trained, providing ramped up volume production
of 300mm wafer bumping and packaging capabilities.
ASE was the first industry player to provide mass production 300mm wafer
packaging,
and remains the industry leader in 300mm wafer flip chip bumping assembly
and test services. ASE offers both printed and electroplated wafer bumping
services for 300mm wafers in-house and has strong 300mm wafer probing
capability with a monthly capacity
of 10,000 wafers.
With qualified processes and comprehensive handling
tools for 300mm wafers, as well
as continued expansion in our various manufacturing sites, ASE has committed
to meeting rigorous customer requirements and fully prepared to address
the latest trends in wafer scale advancements.
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