ASE Group TOP
> Products > Assembly Offerings > CSP > Leadless-LGA
CSPLeadless-LGA
Product
Overview
Land grid array (LGA)
uses laminate substrate to form the landing pad
and the exposed pad for performance enhancement.
It is essentially a BGA minus the solder balls.
LGA's advant-age over other leadless packages is
its flexible routing and multi-chip module capability
LGA is also a thinner (down to 0.66 mm) and lighter
CSP. LGA technology has been developed for lead
free solution and space reduction on mother boards.
This type of package has chip size solution based
on mature laminated substrate technology and material.
Application
LGA is suitable for
high performance ICs like Single Chip, CPU, Logic
and Memory. Common applications for this type of
package includes:
Telecommunication
products
Cellular phone-RF Devices
Wireless LAN
Personal
digital assistants
Personal digital assistants
Digital cameras
IC recorders MP3 players
MP3 players
Memory
card
SD cards
MS cards
PCMCIA
Compact
Features
Thinner, lighter and smaller Chip-Scale Package
Mature standard matrix BGA assembly process
– Higher yield/quality
– Higher through put
– Lower cost
Space reduction at system level
Pb free solution
Excellent electrical and thermal performance
Reliability
Design
Rule
Item
Description
Criteria
(um)
G-A
Exposed
bond finger metal (Double bond)
406
min.
G-B
Exposed
bond finger metal (Single bond)
280
min.
G-C
Max.
bond wire length
5000
um (200 mils) Max.
G-D
Bond
wire center to adjacent bond pad center
50
min.
G-E
Die
bond pad pitch
60
min.
G-F
Bond
wire span over bond finger before target
point
90
min.
G-G
Lead
length in line with bond wire beyond target
point
45
min.
G-H
Bond
wire center to adjacent bond finger (Bottom
die only)
63.5
min.
G-I
Bond
finger width
95
min.
G-K
Wire
center to wire center distance
45
min.
G-L
Wire
bond pad size
60
min.
G-M
Bonding
pad to package edge
1000
min.
Performance
Electrical
Characterization
Unlike
BCC and MCC, some LGA packages have signal traces
to connect the peripheral I/O pads on chip with
array landing pads in the substrate. Thus the electrical
data is not attributed to the gold wire only. Almost
all the LGA substrates are customized. The RLC
data is therefore variable. (Contact ASE R&D
for electrical data.)
Electrical
Ground Path
Thermal
Characterization
(1mm=39.37mil;
1mil=25.4um)
Standard
Process/Materials
Package Offering
Total Thickness (A), Max
1.2
1.1
1.0
0.9
0.8
0.7
0.66
0.5
Remark : Due to sawing type, the package size is flexible by various substrate design or customer request.
Thinner, lighter and smaller Chip-Scale Package
