ASE Global

SiP 3D Package

Product Overview

The need for high density, high performance, and cost effectiveness has sped up the deve-lopment of System on a Chip (SoC) and System in a Package (SiP). The most current assembly technology is the Multi-chip module (MCM) package. It integrates different func-tions of chips such as microprocessors, memory, logic, optic ICs and capacitors, onto mini-substrates, instead of placing individual packages onto a large PCB (also known as second level package).

Application

ASE's MPBGA (Multi Package Ball Grid Array) utilizes the MCM assembly method. It employs the latest IC packaging technology for highdensity products. The electrical and thermal performance and the affordability of the MPBGA package enables system designers to integrate several devices (Known Good Die) onto a single IC package. ASE has been in volume production since Q1, 2002.

The integration of several semiconductor technologies onto a single MPBGA package offers excellent advantages for many applications where size, weight, electrical performance, and board density are critical requirements. The high-speed performance and improved thermal capability of the MPBGA package are also excellent for personal computing, networking, graphic chip, data communication, consumer IC, telecommunication, analog/digital, ASIC, and memory applications.

Features

Known good die

Reduced size and weight

Improved Silicon efficiency

Reduced signal delay & noise

Lower power consumption

Enhanced speed & bandwidth

Excellent electrical performance by shrinking the board level interconnection into a
package level

Customized-design of substrate routing

Space saving

System integration

Reliability

Package Level

Board Level

Design Rule

Item	Criterion
Mold edge to package edge	1 mm min.
Mold edge to CSP edge	0.3 mm min.
CSP edge to package edge	0.1 mm min.
Passive component to package edge	1 mm min.
Fiducial mark for SMT	0.5 mm min.
No. of fiducial mark	2N-1 (N: No. of CSP)
Position of fiducial	Mid-point of two point should be package center
Solder ball edge to package edge	0.6 mm min. (CSP package)

Performance

Electrical Characterization (Contact ASE R&D for details.)

Thermal

Layer	Lead count	Pkg size (mm)
1	488	45x45
2	488	45x45
3	488	45x45
4	972	45x45

Multi Package BGA (MPBGA)

Standard Process/Materials

Wafer Back Grinding (Option)
Wafer Mount
Wafer Saw/Clean
2nd Optical (Gate)
Die Attach	A1 Epoxy: ABLESTIK 2100A; Substrate: BT resin
Epoxy Cure
Wire Bond	Gold wire: 99.99% Au
3rd Optical (Gate)
Mold	M1 Compound: SUMITOMO-7720TA
Post Mold Cure
Top Side Laser Marking	TECA white 460
Ball Mount	Lead free
Reflow
Flux Cleaning
Singulation
Testing
Solder Paste Print	No clean solder paste
Surface Mount
Reflow
Under Fill (Option)	U1
Under Fill cure (Option)
Testing
Final Visual Inspection (Gate)
Packing	Tray or tube

Packing Offering


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