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  • Wafer Level Integration Passive Device Technology

    As miniaturization requirements for electronic devices increase, smaller and lighter SiPs are garnering much attention within the industry. Passive devices such as inductors, capacitors, filters and diplexers are those components occupying the largest real estate of printed circuit board; hence miniaturization and integration is key to advanced SiP. This can be achieved through integrating passive components on an individual substrate using thin film process, known as MCM-D or IPD (Integrated Passive Device). The IPD can then be used as a package substrate or interposer for SiP.

    This lower cost manufacturing method after CMOS process can enhance product performance and also reduce the overall costs. The extension of ASE’s current RDL process can be used to build high quality factor (Q) inductor and RF circuits on top of CMOS wafer.

    Through Wafer Interconnection

    Through Wafer Interconnection (TWI) is a first level interconnection method to inter-connect electrical signal of two stacked dies directly through the silicon. The interconnection is formed with micro-bumps connecting with through silicon vias (TSV). The bonding process can be conducted in either die-to-wafer (DtW) format or wafer-to-wafer (WtW) format.

    The idea was proposed more than 20 years ago and early work can be tracked back to 1990s. Recently, TWI has become an increasingly more critical technology. Application as well as production of this technology for memory stacking and CMOS Image Sensor (CIS) has commenced in recent years.

    TWI comprises TSV technology, double side redistribution layer (RDL) and micro-bumping technology. It provides the advantages of a) shortest signal connection path, thus reducing signal loss and increasing performance; b) Lower power consumption; c) Package size, form factor miniaturization and d) Heterogeneous integration capability. Additionally, the front-end-of-line (FEOL) scaling down has reached the area close to physical limit that it starts to depart from Moore's Law, and the alternative solution from 3D IC stacking become very promising and the major driving force of TWI.

    Applications of TWI mainly focus in 2.5DIC (Si interposer integration) , 3D active die stack and Wafer-Level MEMS (WLMEMS).

    2.5D IC (TSV-Interposer integration)

    An Si interposer with TWI can be used as a platform to bridge the fine pitch capability gap between assembly substrate and integrated circuit board. It can help to keep the pad pitch scaling path without being limited by assembly substrate technology. In addition to the above advantage, integrating GPU, CPU and memory together with decoupling capacitor is also feasible by ASE 2.5DIC (TSV-interposer) solution.

    3D IC (3D Die Stacking)

    3D die (with TWI) stacking provides the ultimately shortest connection path for devices on different chips, as well as the possibility of heterogeneous integration capability make 3D die stack an alternative solution for System-on-Chip (SoC) in application when system complexity and manufacturing process issues inhibit a single chip solution. A remarkable advantage with 3D Die Stacking of Memory on Logic is the high bandwidth layout facilitating wide I/O performance.

    Wafer-Level MEMS

    Another potential application for TWI technology is MEMS packaging. As the package trend for MEMS assembly is migrating from discrete packages to SiP module and Wafer-level integration, which is considered a more efficient process and cost effective solution. Wafer level assembly integrating MEMS device, active device, capping and TWI technology enables the self-contained Wafer-Level MEMS package with a smallest form factor.

    Embedded (Chip) Technology

    Embedded (Chip) Technology is considered an alternative solution to achieve higher level integration with multi-functionalities and form factor shrinkage advantages. There are 2 kinds of processes: (I) chip-first, the chip is buried in the substrate material firstly and followed by the packaging circuit forming processes. (II) chip-last, the chip is not integrated into the packaging process until the circuits on the chip carrier are pre-formed. The chip-last process is known with less KGD yield concern compared with the chip-first one. ASE offers both chip-first and chip-last packaging solutions. There are several different package groups belong to this embedded-chip family:

    (A) aWLP: chip-first, chip embedded in mold compound, fan-out by wafer-level RDL

    (B) aEASI: chip-first, chip embedded in organic dielectric, fan-out by substrate-level RDL

    (C) Laminated FCCSP: chip-last, chip embedded in organic dielectric, fan-out by Flip Chip substrate